1. Field of the Invention
This invention relates generally to computer processing, and, more particularly, to computer central processing unit bus architecture.
2. Description of the Related Art
Performance of computers is greatly affected by the efficiency of internal data transfer within a computer system. One primary factor that affects internal data transfer is the performance of data and address busses that are utilized by the various processors within a computer system. As the capabilities of modern processors become more sophisticated, the implementation of bus systems that carry data to and from the processors must also be enhanced. Performance potential of processors in a computer system may not be realized if the bus systems that support the processors are not implemented properly. Many times, bus systems that feed data and addresses to and from the processors in a computer system can actually cause a xe2x80x9cbottle neckxe2x80x9d effect, slowing down the processing and accessing of data. Delays in accessing data from memory could result in limitations of processor performance. Therefore, efficiency of internal data transfer within computer systems, such as efficiencies in data flow through data busses, is important for optimal performance of computer systems.
Current computer systems that contain multiple processors generally require a plurality of processor busses. Coherency between the multiple data busses within a computer system is important. This is particularly true since processors in most computer system tend to have a relatively large amount of cache memory. Information that is acquired from one data bus may be modified in a cache of a processor and placed on another data bus. Coherency tags are generally used by a host controller to maintain a certain amount of coherency between data busses. To maintain coherency between data busses, generally a number of coherency tag banks are created. Generally, separate tag banks are created for each processor bus within a computer system. The information relating to each processor bus is logged into each coherency tag bank. When an access to a coherency tag bank is required, the host controller checks each coherency tag bank to locate a particular tag that relates to the processor bus.
Accessing and updating coherency information must be done at the highest possible speed. Quite often, there may be more than one coherency tag lookup that is executed per clock cycle. If the coherency tag architecture that is implemented does not have the bandwidth to keep up with the rapid transfer of data, overall performance of the computer system can be compromised. Furthermore, interfaces are generally needed for each new tag bank, which is typically a set of static random access memory (SRAM), requiring more logic and integrated circuit (IC) chip pins, thereby increasing the cost of the associated controller.
Often, a data bus may be more active than another data bus. The imbalance of bus activity could result in a non-symmetrical utilization of coherency tag banks. The non-symmetrical utilization of coherency tag banks could result in unnecessary evictions of tag locations from the coherency tag banks. Unnecessary evictions of tag locations can cause the overall performance of the computer system to be compromised.
The current implementation of coherency tags for multiple processor busses includes a separate bank of coherency tags for each data bus. When a data transfer cycle is implemented on any bus, a coherency tag bank lookup is performed in all coherency tag banks. The same is true when entering updates to the coherency tag information. Since the coherency tag information is generally stored in separate banks with separate corresponding interfaces, access to the coherency tag information is generally performed in parallel.
There are numerous disadvantages associated with the current implementation of coherency tags. One problem with the current implementation of coherency tags is a high cost in bandwidth due to multiple accesses to several coherency tag banks. Each lookup of coherency tag information requires a separate read cycle to each bank. Updates to the coherency tag information generally require a separate write cycle to each coherency tag bank. Even if the separate read and write (update cycles) cycles were performed in parallel to reduce bandwidth costs, an increased number of signal pins on the hardware will be required.
Another problem with the current implementation of coherency tags is a redundancy of coherency tag lines. Often, the coherency state information for the same address will be held in multiple coherency tag banks. The redundancy of the coherency state information results in unused coherency tag line resources.
Furthermore, non-symmetric bus activity can cause imbalanced coherency tag utilization. The coherency tag bank supporting the more active data bus will have much higher utilization, causing more unnecessary evictions than there would have been in a balanced system. Excessive unnecessary eviction of coherency tag information can lead to lower cache hit rates.
Another problem associated with the current implementation of coherency tags is the relatively high cost of expanding to add more data busses. Generally, adding a third processor data bus to a two processor data bus system would require approximately an additional fifty hardware signal pins and associated logic. The additional pins and associated logic will be required to control additional coherency tag banks. This additional cost of more pins and logic would increase the cost of adding an additional processor to a computer system.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for encoding coherency tag information for a plurality of busses. A first processor bus is coupled to a host controller. A second processor bus is coupled to a host controller. The host controller is coupled to a single coherency tag bank. Coherency tag data from the first processor bus and the second processor bus is stored into the coherency tag bank. A location of a data set sought by the first processor and the second processor is determined using the coherency tag data.
In another aspect of the present invention, an apparatus is provided for encoding coherency tag information for a plurality of busses. The apparatus of the present comprises of: at least one left-side processor bus; at least one right-side processor bus; a host controller electrically coupled with the left-side processor bus and the right-side processor bus; and a single coherency tag bank electrically coupled with the host controller.